• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    Three-dimensional chip radio frequency inductor, transformer and amplifier A three-dimensional chip radio frequency inductor, transformer and amplifier are described. the radio frequency amplifier includes a pair of transformers and a transistor. transformers include at least two inductors coupled by induction. inductors include a plurality of segments (704) of a first metallic layer, a plurality of segments (706) and a second metallic layer, a first inductor inlet (708), a second inductor inlet (710) and a plurality of pathways through silicon (702) coupling the plurality of segments of the first metallic layer and the plurality of segments of the second metallic layer to form a continuous path without intersection between the first inductor inlet and the second inductor inlet. inductors can have a symmetrical or asymmetric geometry. the first metallic layer can be a metallic layer in the back-end-of-line section of the chip. the second metallic layer can be located on the chip's redistributed design layer.
    公开号:BR112012007822B1
    申请号:R112012007822
    申请日:2010-10-07
    公开日:2020-04-07
    发明作者:Matthew Henderson Brian；Kim Jonghae；G Chua-Eoan Lew；Nowak Matthew；S Bazarjani Seyfollah；Gu Shiqun；R Toms Thomas
    申请人:Qualcomm Inc；
    IPC主号:
    专利说明:

    “THREE-DIMENSIONAL CHIP INDUCER, TRANSFORMER AND AMPLIFIER IN THREE-DIMENSIONAL CHIP
    Field of the Invention [0001] The present description generally relates to integrated circuit devices, and, more particularly, to inductors and transformers implemented in an integrated circuit device via tracks. Background [0002] Inductors and transformers are used in a wide variety of integrated circuit applications including radio frequency integrated circuit (RF) applications. A chip inductor is a passive electrical component that can store energy in a magnetic field created by the current that passes through it. An inductor can be a conductor shaped like a coil that includes one or more turns. The loops concentrate the magnetic field flow induced by the current flowing through each loop of the conductor in an inductive area within the loops of the inductor. The number of turns and the size of the turns affect the inductance.
    [0003] Two (or more) inductors that coupled a magnetic flux form a transformer. A transformer is a device that transfers electrical energy from one circuit to another through inductively coupled conductors, usually the coils or loops of the inductors that form the transformer. A variable current in a first inductor or primary inductor induces a variable voltage in a second inductor or secondary inductor. If a load is coupled to the secondary inductor, current will flow in the
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    2/29 secondary inductor and electrical energy will flow from the primary circuit through the transformer to the load.
    [0004] Conventional inductors implemented in integrated circuit arrays and circuit packs can have several disadvantages. These inductors can be made by helical formation or spiral residues in conductive layers to form inductive loops. In some cases, these residues can be coupled to residues in adjacent layers in order to achieve greater inductance. Unfortunately, inductors can consume excessive metallic layer resources and may not provide sufficient current capacity or a high enough quality factor without undesirable scaling. Additionally, since the inducting areas of the inductors are substantially parallel with respect to other layers of residue on the package substrate and circuit matrix, they may have unfavorable electromagnetic interference (EMI) effects on other components within the integrated circuit and / or its inductive characteristics can be adversely affected by adjacent conductors within the substrate or circuit matrix.
    [0005] Figure 1 illustrates a cross section of CMOS 100 technology that includes three sections: a Redistributed Design Layer (RDL) 102 section, a Line frontend (FEOL) section 104, and a back- end-of-Line (BEOL) 106. The FEOL 104 section includes a substrate 108 and the BEOL 106 section includes a plurality of metallic layers M1-Mn. The height or thickness 114 of the FEOL 104 section is usually much greater than the height or thickness 110 of the BEOL 106 section. The metallic layers of the BEOL 106 section that
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    3/29 are close to substrate 108 are used for interconnections between devices, and conventional inductors can induce unwanted coupling with the surrounding layers. Thus, to provide space for interconnections and to minimize unwanted coupling caused by conventional inductors, an available height of inductor 112 in the BEOL section 106 away from substrate 108 is less than the total height 110 of the BEOL section 106. Conventional, inductors on the chip are normally manufactured using a two-dimensional geometry in one or more of the metallic layers M1-Mn in the section BEOL 106.
    [0006] A top view of an illustrative symmetrical loop inductor 200 having two input ports 202, 204 is illustrated in figure 2. Symmetric inductor 200 can be divided by a line of symmetry 206 so that a first half of the inductor 208 on one side of the line of symmetry 206 has the same dimensions as a second half of inductor 210 on the other side of line of symmetry 206. However, since the inductance value is proportional to the total length of the metallic line used to form the inductor, the one-inductor geometry of the symmetrical inductor 200 has an inductance disadvantage since it only has a single revolution. Additional turns or metallic length can increase the inductance value.
    [0007] The dimension ratio between an inductor on the conventional chip and a transistor can provide an appreciation of the relatively excessive metallic layer resources that can be consumed by an inductor in a BEOL metallic layer. A conventional chip inductor can occupy an area
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    4/29 of 300 μη x 300 μη or an area of 90,000 μη 2 . In contrast, using an available characteristic size, a transistor can occupy an area of 0.09 μm 2 . Thus, the chip size ratio between the space consumed by the inductor and the transistor is 1,000,000: 1. Additionally, due to the staggering of CMOS technology, the chip cost per mm 2 continues to increase as the BEOL for passive devices does not scale while the FEOL for active devices scale. Thus, the chip cost of an inductor or transformer is very high and should increase in nodes with more advanced technology, for example, 45 nm or 32 nm.
    [0008] A top view of an illustrative spiral multi-turn inductor 300 is illustrated in figure 3. The spiral architecture can be used to increase the inductance value. The spiral multiple loop inductor 300 does not have symmetry equal to the one loop inductor 200, but has an increased inductance value due to the increased total metal length. The lack of symmetry provides the polarity inputs of inductor 300. Since the inductance value of inductor 300 is proportional to the total series metal length used to form inductor 300, the inductance value is affected by the width of the metal conductor forming the inductor loops, the space between the loops, the diameter of the metallic conductor and the number of loops in the spiral. The inputs for inductor 300 are normally brought to the same side of the inductor structure. The multi-spiral coil inductor 300 includes a multi-spiral coil part 302, a first inlet 304 and a second inlet 306 which is brought from the end point of coil 308 to the same side as the inductor
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    5/29
    300 than the first inlet 304. A wire 310 is used to bring the second inlet 306 out of the end point of spiral 308 of inductor 300. In this configuration, the multi-turn inductor 300 has some disadvantages with respect to the one-turn inductor 200 The multi-turn inductor 300 needs two metallic layers: a metallic layer for the first inlet 304 and a spiral part 302 to increase the inductance; and a second metallic layer for the wire 310 to bring the second inlet 306 out of the end point of the spiral 308. In contrast, the one-loop inductor 200 can be implemented in a metallic layer. The spiral multi-turn inductor 300 also has overlapping regions 312 and 314 due to its multi-turn portion 302 that cracks the wire 310 which can cause a capacitive coupling between the layers. This capacitive coupling of these overlapping regions 312, 314 can degrade the performance of inductor 300.
    [0009] Since the metallic layers M1-Mn are also used for interconnections between devices and other purposes in addition to creating inductors, such as inductors 200 and 300, the available height of inductor 112 is less than the total height 110 of the BEOL section 106. These types of inductors also induce unwanted coupling of surrounding layers. To reduce coupling to the substrate, these types of inductors are usually placed in higher metallic layers. In addition, other devices or interconnections in the same metallic layer as inductors 200 or 300 are separated from the inductor by an insulating distance, for example, 100 microns, to prevent magnetic coupling between the inductor and the others
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    6/29 devices or interconnections. This isolation distance is determined by the required isolation of circuits from the magnetic field of the inductors, and adds to the area consumed by the inductor, and thus increases the cost of the matrix.
    [0010] A conventional method of further increasing the total metallic length of an inductor is the stacking of a series of metals. Figure 4 illustrates an inductor 400 that includes three different metallic layers 402, 404, 406 that are formed in the metallic layers M1-Mn of the section BEOL 106. The metallic layers 402 and 404 are separated by a distance 412, and the metallic layers 404 and 406 are separated by a distance 414. The metal layers 402, 404, 406 are connected in series by vertical connectors 408 and 410. The three-layer inductor 400 has a first entry 416 in the metal layer 402 and a second entry 418 in the layer metal 406. The second inlet 418 can be brought out to the same side of the inductor structure as the first inlet 416 using a metallic wire in another layer similar to the wire 310 shown in figure 3. The distances 412, 414 between the layers metal 402, 404, 406 are very small (for example, 2 to 3 μη) with respect to the diameter of the spiral shapes (for example, 200 μη) in each of the metal layers 402, 404, 406. Thus, the The lengths of the vertical connectors 408 and 410 only contribute a negligible amount to the total length of the inductor. The total metal length of inductor 400 is approximately 3 times greater than the total metal length of inductor 300. However, the three-layer inductor 400 conventionally has a value
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    7/29 inductance which is less than 3 times the inductance value of inductor 300 since the total inductance is reduced due to the cancellation of the magnetic field between the multiple layers. Thus, the ability to increase the inductance value using metal stacking is limited due to the process restrictions for the BEOL 106 section.
    [0011] Note that for any of the above inductor configurations, the inductance is a function of the total metal inductor length. In this way, the size of the inductor is the same regardless of the technology. Each metallic layer used for these inductors can alternatively provide space for billions or more transistors. Additionally, since the inductive areas of the inductors are substantially parallel with respect to other residual layers, they may have unfavorable EMI effects on other components within the integrated circuit and / or their inductor characteristics may be adversely affected by the adjacent conductors.
    [0012] These problems for inductors are multiplied in the case of transformers that are made of two or more inductors. An illustrative implementation of a transformer 500 in the BEOL section of a chip is illustrated in figure 5. The chip includes a BEOL 502 section, where transformer 500 is implemented, and a FEOL 504 section. The FEOL 504 section includes substrate 506 and several upper layers deposited on top of substrate 506 for coating and other purposes where the active devices of the chip are normally located. Transformer 500 includes a first inductor 510 and a second inductor 512 which are
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    8/29 inductively coupled. In this implementation, the metallic layers in the BEOL 502 section become progressively thicker to tune the inductance values of the first inductor 512 and the second inductor 512. For clarity, the right side of figure 5 illustrates a symbolic representation of the transformer 500. The first inductor 510 has a first input P1 for connection to a circuit on the chip and a second input coupled to ground. The second inductor 512 has a first input P2 for connection to another circuit on the chip and a second input that is also coupled to the ground. The symbolic representation also illustrates the inductor coupling on transformer 500 between the first inductor 510 and the second inductor 512. Similar to the inductors illustrated above, this transformer implementation consumes a significant amount of area which is very expensive.
    [0013] Thus, it would be desirable to have a new type of inductor for use in transformers and integrated circuits that can create higher inductance values in less space, that can take advantage of smaller accessory size advances, or that may have fewer effects of electromagnetic interference on other components within the integrated circuit.
    Summary [0014] A three-dimensional chip inductor using pathways through silicon (TSVs) can be used in integrated circuits and transformers. The three-dimensional chip inductor can create greater inductance in less space and thereby free up a portion of valuable chip resources. The three-dimensional chip inductor can take
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    9/29 advantage of smaller accessory size advances and shrink with new technologies. The three-dimensional chip inductor has a vertical appearance due to the integration of pathways through silicon and may have less electromagnetic interference effects on other components within the integrated circuit: The pathways through the three-dimensional chip inductor silicon can also be protected to reduce effects of electromagnetic interference on the surrounding components.
    [0015] The three-dimensional chip inductor includes a plurality of segments of a first metallic layer, a plurality of segments of a second metallic layer, a first inductor inlet, a second inductor inlet, and a plurality of pathways through the coupling silicon the plurality of segments of the first metallic layer and the plurality of segments of the second metallic layer. The plurality of paths through the silicon and segments form a continuous and uninterrupted path between the first inductor input and the second inductor input. The first metallic layer can be a metallic layer in the back-end-of-line section of the chip. The second metallic layer can be located on a redistributed design layer of the chip.
    [0016] The three-dimensional chip inductor can have a symmetrical or asymmetric geometry. In symmetric geometry, the first and second inductor inputs are located in one of the first metallic layer and the second metallic layer, and the chip inductor has a symmetric geometry around a line of symmetry that passes between the first and second inductor inputs. In
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    10/29 an asymmetric geometry, the first inductor inlet is located in one of the first metallic layer and the second metallic layer, and the second inductor inlet is located in another metallic layer.
    [0017] The plurality of pathways through silicon can be distributed in a regular arrangement pattern. The pattern of regular arrangement of pathways through silicon can be surrounded by a perimeter comprising a plurality of grounded pathways through silicon, where the plurality of pathways through grounded silicon is coupled to earth. These grounded silicon pathways can significantly reduce the electromagnetic interference by the inductor in the surrounding devices on the chip.
    [0018] A three-dimensional chip transformer is also described. The three-dimensional chip transformer includes a first chip inductor and a second chip inductor. Each of the first and second chip inductors includes a plurality of first segments in a first metallic layer, a plurality of second segments in a second metallic layer, a first inductor inlet, a second inductor inlet, and a plurality of pathways through of the silicon coupling the plurality of first segments and the plurality of second segments to form a continuous path without intersection between the first inductor input and the second inductor input. The first chip inductor is inductively coupled to the second chip inductor, and the first chip inductor is not physically coupled to the second chip inductor except through ground. The first and second inductor inputs can be located in one of the first metallic layer and the second layer
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    11/29 metallic. The first metallic layer can be one of the metallic layers in the back-end-of-line section of the chip. The second metallic layer can be located on a redistributed design layer of the chip. The plurality of pathways through the silicon of the first chip inductor can be distributed in a regular arrangement pattern, and the plurality of pathways through the silicon of the second chip inductor can be distributed in a regular arrangement pattern. Pathways through silicon can also be protected to reduce electromagnetic interference in the surrounding devices.
    [0019] A three-dimensional chip radio frequency amplifier is also described. The three-dimensional chip radio frequency amplifier includes a first chip transformer, a second chip transformer, and a first chip transistor. The first chip transformer includes a first chip inductor and a second chip inductor. The second chip transformer includes a third chip inductor and a fourth chip inductor. The first chip transistor includes a port, a drain and a source. Each of the first, second, third and fourth chip inductors includes a plurality of first segments in a first metallic layer; a plurality of second segments in a second metallic layer; a first inductor inlet, a second inductor inlet, and a plurality of pathways through the silicon coupling the plurality of first segments and the plurality of second segments to form a path without continuous intersection between the first inductor inlet and the second inlet inductor. The first chip inductor is coupled by induction to the second chip inductor, the third inductor
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    12/29 chip is inductively coupled to the fourth chip inductor, and the first, second, third and fourth chip inductors are not physically coupled to each other except across the ground. The first inductor input of the second chip inductor is coupled to the port of the first chip transistor. The first inductor input of the third chip inductor is coupled to the drain of the first chip transistor. The second inductor input of the first, second, third and fourth chip inductors is coupled to the ground. The source of the chip transistor is coupled to the ground. The first and second inductor inputs can be located on one of the first metallic layer and the second metallic layer. The first metallic layer can be a metallic layer in the line's back-end section of the chip. The second metallic layer can be located on a redistributed design layer of the chip. The plurality of pathways through the silicon of each of the chip inductors can be distributed in a regular arrangement pattern and can be protected.
    [0020] The three-dimensional chip amplifier can also include a fifth inductor, a sixth inductor and a second chip transistor that includes a port, a drain and a source. The port of the second chip transistor can be coupled to the drain of the first chip transistor .; the drain of the second chip transistor can be coupled to the first inductor input of the third chip inductor, the source of the second chip transistor can be coupled to ground; the first inductor inputs of the fifth and sixth chip inductors can be coupled to a supply voltage; the second inductor input of the fifth inductor can be coupled to the drain of the first chip transistor; and the second
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    13/29 inductor input of the sixth inductor can be coupled to the drain of the second chip transistor. Each of the fifth and sixth chip inductors can include a plurality of first segments in a first metallic layer, a plurality of second segments in a second metallic layer and a plurality of pathways through the silicon coupling the plurality of first segments and the plurality of second segments to form a continuous, non-intersecting path between the first inductor input and the second inductor input of the fifth and sixth inductors, respectively. The first and second inductor layers of the fifth inductor are located in one of the first layer
    metallic and the second layer metallic. At first and Monday layers of sixth inductor inductor are located without one among the first layer metallic and the second layer metallic.
    [0021] For a more complete understanding of this description, reference is now made to the detailed description below and the attached drawings.
    Brief Description of the Drawings [0022] Figure 1 is a schematic of a cross section of a CMOS device;
    [0023] Figure 2 is a schematic top view of a symmetrical two-dimensional inductor;
    [0024] Figure 3 is a schematic top view of a two-dimensional asymmetric spiral inductor;
    [0025] Figure 4 is a schematic perspective view of an asymmetric two-dimensional spiral inductor in three layers;
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    14/29 [0026] Figure 5 is a schematic cross section of a CMOS device that includes a transformer;
    [0027] Figure 6 is a schematic front view of a cross section of a CMOS device illustrating the pathways through silicon connecting conductive segments in the first metallic layer of the back-end-of-line section to conductive segments in the RDL section;
    [0028] Figure 7 is a schematic top view of an asymmetric three-dimensional chip inductor;
    [0029] THE figure 8 is a View two-dimensional upper simplified of symmetrical three-dimensional inductor figure co 7 illustrating your symmetry; [0030] THE figure 9 is an seen in perspective schematic chip inductor three-dimensional symmetrical figure 7;[0031] THE figure 10 is an seen in perspective
    schematic of a three-dimensional asymmetric chip inductor illustrating its coupling to a circuit on the chip substrate;
    [0032] Figure 11 illustrates a three-dimensional matrix stacking technique for interconnecting two matrices;
    [0033] Figure 12 illustrates a transformer;
    [0034] Figure 13 is a schematic perspective view of a three-dimensional chip transformer;
    [0035] Figure 14 illustrates a radio frequency amplifier;
    [0036] Figure 15 is a schematic perspective view of a three-dimensional chip radio frequency amplifier;
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    15/29 [0037] Figure 16 illustrates a two-stage amplifier that can be implemented with both three-dimensional inductors and three-dimensional transformers; and [0038] Figure 17 is a block diagram illustrating an illustrative wireless communication system in which a three-dimensional inductor transformer or other devices based thereon can be advantageously employed.
    Detailed Description [0039] Similar to figure 1, figure 6 illustrates a cross section of CMOS 600 technology that includes three sections: an RDL 602 section, a FEOL 604 section and a BEOL 606 section. The FEOL 604 section includes a 609 substrate with several upper layers for active devices and the BEOL 606 section includes a plurality of metal layers M1-Mn of which a part 610 is available for conventional inductors. The height of the FEOL 604 section is much greater than the height available for 610 inductors in the BEOL 606 section. In a non-limiting illustrative embodiment, the FEOL 604 section can have a height of the order of 200 μm while the height available for 610 inductors in the BEOL 606 section can be on the order of 10 pm.
    [0040] Figure 6 also illustrates an exploded front view of an illustrative embodiment of an inductor 620 that includes the integration of a plurality of vertical pathways through silicon (pathways through silicon) 622. Inductor 620 is basically located in the FEOL section 604 of CMOS 600 technology and extends into RDL 602 section and BEOL 606 section as explained below. Pathways through silicon 622 pass through substrate 608 and couple the RDL section
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    16/29
    602 and the Ml layer of the BEOL 606 section. The TSV 630 height can be fifty times greater than the available height of inductor 610 in the BEOL 606 section. Paths through silicon 622 increase the total length of inductor 620 which increases the value of inductance, since the serialized length of the inductor is directly proportional to the inductance value. The top of each TSV can be coupled to other routes through silicon with metal segments 626 in the metal layer M1 and the bottom of each TSV can be coupled to other routes through silicon with metal segments 624 in section RDL 602 in a three-dimensional geometry such as illustrated in figure 6.
    [0041] Conventional designs on conventional two-dimensional chips, such as inductors 200, 300 and 400, are limited to increase the inductance density by increasing the inductor area since the distances between the metallic layers in BEOL are negligible. For example, the distances 412, 414 between the metal layers 402, 404, 406 can be 2 to 3 μm while the diameter of the spiral shapes in each of the metal layers 402, 404, 406 can be 200 to 300 pm. Therefore, the design of conventional inductor is effectively limited to two-dimensional optimization. With the integration of pathways through silicon into the inductor design, both the vertical height of the pathways through silicon, for example, 200 pm, and the horizontal slope of the segments connecting the pathways through silicon, for example, 20 pm, can be significant. Therefore, TSV inductors can be designed and optimized in 3 dimensions.
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    17/29 [0042] TSV inductors can also exhibit substantially symmetrical geometry. Figure 7 illustrates a top view of an illustrative inductor 700. Inductor 700 includes a plurality of pathways through silicon 702 passing through a substrate, a plurality of M1 segments 704 in layer M1 of the BEOL section, and a plurality of RDL segments 706 in the RDL section. Inductor 700 also includes a pair of 708, 710 inductor inputs. Note that inductor 700 is designed in three dimensions; so that the M1 segments 704 and the RDL 706 segments are separated vertically by the thickness or height of the FEOL section 604 through which the pathways through silicon 702 pass. Inductor 700 has a symmetrical design. Figure 8 illustrates a simplified two-dimensional format 800 of inductor 700 to illustrate the symmetry of inductor 700 around a central line passing between the inputs of inductor 708, 710.
    [0043] This three-dimensional TSV inductor can, therefore, provide advantages in inductance and symmetrical geometric density. The three-dimensional inductor can have a symmetrical structure through a symmetrical connection of a regular TSV set with RDL and M1 interconnections, and the symmetrical positioning of the inductor inputs. The inductance density is also increased by the vertical height of the pathways through the silicon.
    [0044] Figure 9 illustrates a three-dimensional view of inductor 700, including the plurality of pathways through silicon 702 passing through the substrate, the plurality of M1 segments 704 in the M1 layer of the BEOL section, the plurality of RDL segments 706 in the RDL section. , and the pair of inputs
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    18/29 inductor 708, 710. Note that TSV heights and segment lengths are not drawn to scale. Illustrative TSV heights can include 50 µm or 200 µm, and illustrative connector lengths can be 20 µm or 50 µm. In order to minimize interference with the surrounding devices, inductor 700 can be surrounded by a similarly spaced square of pathways through silicon coupled to the ground. Other known methods for minimizing electromagnetic interference can also be used.
    [0045] As an example and not for the purpose of limitation, an illustrative inductor with the structure of inductor 700 can
    Tue an TSV height in 100 pm, a diameter in TSV in 20 pm, and M1 and RDL common length in 20 pm. O inductor 700 has 64 ways through silicon, 32 segments M1 and 31 RDL segments. Thus, an embodiment with at
    the above illustrative dimensions will have a total inductor length of 64 * 100 + (32 + 31) * 20um which is equal to 7.66 mm; and it will have a horizontal cross section of approximately 90 μm. The inductance value of this embodiment is about 12nH. In contrast, the spiral inductor 300 in figure 3, with an illustrative horizontal cross-section of 200um xs 200 um occupies more than 4 times the area of the three-dimensional TSV inductor, and depending on the thickness and spacing of the residue, it will typically have an inductance of about 0.64 nH.
    [0046] Figure 10 illustrates a three-dimensional view of an alternative non-symmetric inductor 1000. Inductor 1000 includes a plurality of pathways through silicon 1002, a plurality of M1 segments 1006 in layer M1 of the BEOL section.
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    19/29 (bottom), and a plurality of RDL segments 1004 in the RDL section (top). Inductor 1000 also includes a first inductor input 1008 and a second inductor input 1010 in the BEOL section. The top part of figure 10 illustrates the inductor 1000 removed from the chip, and the bottom part of the figure illustrates the connections to the inductor inputs 1008, 1010. The first inductor input 1008 is coupled to the TSV 1012, and the second inductor input 1010 is coupled to TSV 1014. Note that inductor 1000 has an asymmetric spiral shape. Inductor inputs 1008, 1010 are coupled to circuitry 1018 on substrate 1016. Paths through silicon 1002 also pass through substrate 1016. M1 segments 1006 are in layer M1 of the BEOL section and at least inductor input 1010 coupled to the central TSV 1014 is in another metallic layer of the BEOL section. The circuitry 1018 can then be coupled to one or more metallic layers in the BEOL section.
    [0047] Figure 11 illustrates a three-dimensional matrix stacking method to obtain a higher density with inductors and transformers. The matrix stacking technique begins with a first matrix 1100 in block 100 on the upper left side of figure 11, and a second matrix 1150 in block 105 on the right side of figure 11.
    [0048] The first matrix 1100 includes a BEOL section 1102 and a section FEOL 1104. Section FEOL 1104 includes a substrate 1108 and upper layers 1110 where a plurality of active devices are implemented. The BEOL section 1102 includes a plurality of metallic layers including a first metallic chamber 1112 closer to substrate 1108 and an upper metallic layer 1106 further away from
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    20/29 substrate 1108 where at least one metallic layer includes an inductor. The BEOL section 1102 is on the front (FS) side of the first array 1100 and the substrate 1108 of the section FEOL 1104 is currently on the rear side (BS) of the first array 1100.
    [0049] Block 101 illustrates a TSV 1120 entrenched through the upper layers 1110 and a part of substrate 1108 from section FEOL 1104. In that block, substrate 1108 has a thickness t1. The top of the TSV 1120 is coupled to the first metallic layer 1112 in the BEOL 1102 section.
    [0050] Block 102 illustrates the first matrix 1100 after the thinning of the substrate. The substrate thinning process reduces the thickness of the substrate 1108 from thickness t1 to thickness t2. The substrate thinning process exposes the bottom end of TSV 1120 to the bottom of substrate 1108.
    [0051] Block 103 illustrates the first array 1100 after adding an RDL 1130 layer to the bottom of substrate 1108. The RDL 1130 section is now on the rear side of the first array 1100. The RDL 1130 section includes conductors that couple the bottom end from TSV 1120 to a signal input 1132 on the rear side of matrix 1100 forming a conducting path from signal input 1132 through section RDL 1130 and TSV 1120 to the first metallic layer 1112 in section BEOL 1102.
    [0052] Block 104 illustrates the change of the first matrix 110 so that the metallic layers of the beautiful section 1102 on the front side of the first matrix 1100 are now
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    21/29 at the bottom, and the RDL 1130 section at the rear of the first 1100 array is now at the top.
    [0053] Block 105 illustrates the second matrix 1150 which includes a BEOL 1152 section and a FEOL 1154 section. The BEOL 1152 section includes a plurality of metallic layers including an upper metallic layer 1156 furthest from substrate 1158 where at least one metallic layer includes an inductor. The FEOL 1154 section includes a substrate 1158 and upper layers 1160 where a plurality of active devices are implemented. The BEOL 1162 section is in the FS of the second matrix 1150 and the substrate 1158 of the FEOL 1154 section in the BS of the second matrix 1150.
    [0054] Block 106 illustrates the change of the second matrix 1150 so that the metallic layers of the BEOL 1152 section on the front side of the second matrix 1150 are now on the bottom, and the substrate 1158 on the rear side of the second matrix 1150 are now on top .
    [0055] Block 107 illustrates the connection of the front side of the second matrix 1150 to the rear side of the first matrix 1100 using a micro projection 1140. The micro projection 1140 provides a conductive path coupling the signal input 1132 of the RDL 1130 section on the side rear of the first matrix 1100 with the upper metallic layer 1156 in the section BEOL 1152 on the front side of the second matrix 1150.
    [0056] Thus, this three-dimensional matrix stacking technique provides a conductive path that can be used to couple an inductor or transformer in the upper metallic layers 1156 of the second matrix 1150 to the first metallic layer 1110 of the first matrix 1100 through
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    22/29 of the metal projection 1140 and through the RDL 1130 and TSV 1120 sections of the first matrix 1100.
    [0057] Figure 12 illustrates a transformer 1200 that includes a first inductor 1202 and a second inductor 1204. The inductance value is basically proportional to the length of the inductor and a transformer requires two inductors plus a larger chip area for the coupling structure electromagnetic. The first inductor 1202 has a first input 1208 and a second input 1210; the first input 1208 can be coupled to a primary circuit (not shown) and the second inductor input 1210 is coupled to ground. The second inductor 1204 has a first inlet 1212 and a second inlet 1214; the first input 1212 can be coupled to a load (not shown) and the second inductor input 1214 is coupled to ground. The first inductor 1202 is physically separated from the second inductor 1204 in a way that promotes electromagnetic coupling 1206 between the two inductors so that a variable current in the first inductor 1202 induces a variable voltage in the second inductor 1204 which causes energy to flow from the primary circuit through transformer 1200 for the load. Different materials can be used to improve the coupling coefficient within transformer 1200, for example, ferromagnetic materials. Some illustrative ferromagnetic materials that can improve the coupling coefficient include nickel, cobalt, iron and mu-metal.
    [0058] Figure 13 illustrates an illustrative implementation of a 1300 transformer using inductors that include pathways through silicon. The 1300 transformer
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    23/29 includes a first inductor 1310 and a second inductor 1320. Each of the first inductor 1310 and second inductor 1320 includes a plurality of pathways through silicon 1302 that pass through the substrate of a chip (see, for example, figure 6) which are coupled to the upper end by the M1 1306 segments in the M1 layer of the BEOL section and at the lower end by the RDL 1304 segments in the RDL section to form a continuous path. The first inductor 1310 has a first input 1312 and a second input 1314; the first input 1312 can be coupled to a primary circuit (not shown) and the second inductor input 1314 is coupled to ground. The second inductor 1320 has a first input 1322 and a second input 1324; the first input 1322 can be coupled to a load (not shown) and the second inductor input 1324 is coupled to ground. The first inductor 1310 is physically separated from the second inductor 1320 by dielectric material in order to promote the electromagnetic coupling between the two inductors. Pathways through silicon passing through the substrate increase the length of the inductor which increases the inductance value. The alternative connection of pathways through silicon by RDL and M1 segments in a continuous path forms in a chip inductor, and the pair of these TSV inductors forms a transformer.
    [0059] An illustrative application of a transformer is in an RF amplifier 1400, illustrated in figure 14, which can be used in RF integrated circuits. The RF amplifier 1400 includes a first transformer 1402 and a second transformer 1404 coupled together by a transistor 1406. Transistor 1406 has a port 1401,
    Petition 870190090562, of 12/09/2019, p. 33/47
    24/29 a source 1412 and a drain 1414. The source 1412 of transistor 1406 is coupled to ground.
    [0060] The first transformer 1402 includes a first inductor 1420 that is inductively coupled to a second inductor 1422. The first inductor 1420 has a first input 1424 and a second input 1426; the first input 1424 can be coupled to an RF input and the second inductor input 1426 is coupled to ground. The second inductor 1422 has a first inlet 1428 and a second inlet 1430; the first input 1428 is coupled to port 1410 of transistor 1406 and the second inductor input 1430 is coupled to ground.
    [0061] The second transformer 1404 includes a third inductor 1440 coupled by induction to a fourth inductor 1442. The third inductor 1440 has a first input 1444 and a second input 1446; the first inductor input 1444 is coupled to drain 1414 of transistor 1406 and the second inductor input 1446 is coupled to ground. The fourth inductor 1442 has a first inlet 1448 and a second inlet 1450; the first input 1448 can be used as an RF output and the second inductor input 1450 is coupled to ground. Transformers 1402 and 1404 perform the roles of signal coupling and impedance transformation due to the back-to-back ratios between their inductors.
    [0062] Figure 15 illustrates an illustrative implementation of an RF amplifier 1500 using inductors that include pathways through silicon. The RF amplifier 1500 includes a first transformer 1502 and a second transformer 1504 coupled together by a transistor 1506. Transistor 1506 has a port 1510, a source 1512 and a
    Petition 870190090562, of 12/09/2019, p. 34/47
    25/29 drain 1514. The source 1512 of transistor 1506 is coupled to ground.
    [0063] The first transformer 1502 includes a first inductor 1520 which is coupled by induction to a second inductor 1522. Each of the first inductor 1520 and second inductor 1522 includes a plurality of pathways through the silicon that pass through the substrate of a chip where the pathways through silicon are coupled at the top end by segments in the m1 layer of the BEOL section and at the bottom end by segments in the RDL section to form a continuous path (see, for example, figure 12). The first inductor 1520 has a first inlet 1524 and a second inlet 1526; the first input 1524 can be coupled to an RF input and the second input 1526 is coupled to ground. The second inductor 1522 has a first inlet 1528 and a second inlet 1530; the first input 1528 is coupled to port 1510 of transistor 1506 and the second inductor input 1530 is coupled to ground.
    [0064] The second transformer 1504 includes a third inductor 1540 that is inductively coupled to the fourth inductor 1542. Each of the third inductor 1540 and fourth inductor 1542 includes a plurality of pathways through the silicon that pass through the chip substrate where the pathways through silicon they are coupled at the top end by segments in the M1 layer of the BEOL section and at the bottom end by segments in the RDL section to form a continuous path (see, for example, figure 13). The third inductor 1540 has a first inlet 1544 and a second inlet 1546; the first input 1544 is coupled to drain 1514 of transistor 1506 and the second input 1546 is coupled to ground. The fourth inductor 1542 has a first input 1548 and a
    Petition 870190090562, of 12/09/2019, p. 35/47
    26/29 second entry 1550; the first input 1548 can be used as an RF output and the second input 1550 is coupled to ground.
    [0065] Inductors and transformers using pathways through silicon can be used in several other applications, another example being a two-stage amplifier 1660, illustrated in figure 16. The amplifier 1600 includes a first transformer 1602 and a second transformer 1604, both which may include TSV inductors as described above. The first transformer 1602 and the second transformer 1604 are coupled via a first transistor 1606 and a second transistor 1608. The first transistor 1606 includes a port 1662, a drain 1664, and a source 1666. The second transistor 1608 includes a port 1682, a drain 1684, and a source 1686. The drain 1664 of the first transistor 1606 is coupled to a supply voltage VDD through a first inductor 1610, and the drain 1684 of the second transistor 1608 is coupled to the supply voltage VDD through a second inductor 1612. The first inductor 1610 or the second inductor 1612 can also be a TSV inductor as described above.
    [0066] The first transformer 1602 includes a first inductor 1620 which is coupled inductively to a second inductor 1622. The first inductor 1620 has a first input 1624 and a second input 1626. The second inductor 1622 has a first input 1628 and a second input 1630. The first input 1624 of the first inductor 1620 is coupled to the signal input for amplifier 1600. The first input 1628 of the second inductor 1624 is coupled to port 1662 of the first transistor 1606 through a first
    Petition 870190090562, of 12/09/2019, p. 36/47
    27/29 capacitor 1632. The second input 1626 of the first inductor 1620 and the second input 1630 of the second inductor 1622 are both coupled to ground.
    [0067] Port 1662 of the first transistor 1606 is also coupled to the supply voltage Vdd through a resistor 1634. Port 1682 of the second transistor 1608 is coupled to drain 1664 of the first transistor 1606. The source 1666 of the first transistor 1606 and source 1686 of the second transistor 1608 are both grounded.
    [0068] The second transformer 1604 includes a first inductor 1640 coupled by induction to a second inductor 1642. The first inductor 1640 has a first input 1644 and a second input 1646. The second inductor 1642 has a first input 1648 and a second input 1650 The first input 1644 of the first inductor 1640 is coupled to drain 1684 of the second transistor 1608 through a second capacitor 1636. The first input 1648 of the second inductor 1642 can be used as an output of the two-stage amplifier 1600. The second input 1646 of the first inductor 1640 and the second input 1650 of the second inductor 1642 are both coupled to ground. Transformers 1602 and 1604 perform the roles of signal coupling and impedance transformation due to the back-to-back ratios between their inductors.
    [0069] Figure 17 illustrates an illustrative wireless communication system 1700 where an embodiment of an inductor or transformer implemented using a plurality of pathways through silicon can be advantageously employed, where paths through silicon are interconnected to form a path of continuous driving using segments
    Petition 870190090562, of 12/09/2019, p. 37/47
    28/29 conductors in a metallic layer of the BEOL section and conductive segments in the RDL section of a matrix. Inductors implemented using Vias through silicon can have a symmetric or asymmetric geometry. For purposes of illustration, figure 17 illustrates three remote units 1720, 1730, 1750 and two base stations 1740. It should be recognized that typical wireless communication systems may have more remote units and base stations. Any of the 1720, 1730, 1750 remote units can include a memory power management system supporting multiple power modes as described here. Figure 17 illustrates forward link signals 1780 from base stations 1740 and remote units 1720, 1730 and 1750 and reverse link signals 1790 from remote units 1720, 1730 and 1750 to base stations 1740.
    [0070] In figure 17, remote unit 1720 is illustrated as a mobile phone, remote unit 1730 is illustrated as a portable computer, and remote unit 1750 is illustrated as a remote unit with fixed location in a local wireless circuit system . For example, remote units can be cell phones, PCS units, portable data units such as personal data assistants, or fixed location data units such as meter reading equipment. Although figure 17 illustrates certain illustrative remote units that may include a memory power management system supporting multiple power modes as described here, the memory power management system is not limited to these illustrative illustrated units. The embodiments can be properly employed in
    Petition 870190090562, of 12/09/2019, p. 38/47
    29/29 any electronic device where a memory power management system supporting multiple power modes is desired.
    [0071] While illustrative embodiments incorporating the principles of the present invention have been described above, the present invention is not limited to the described embodiments. Instead, this application must cover any variations, uses or adaptations of the invention using its general principles. In addition, this application is intended to cover such distances from the present description that are known or common practice in the art to which this invention belongs and which are within the limits of the appended claims.
    权利要求:
    Claims (6)
    [1]
    1. Three-dimensional chip inductor comprising:
    a plurality of segments of a first metallic layer;
    a plurality of segments of a second metallic layer;
    a first inductor input and a second inductor input;
    the three-dimensional chip inductor characterized by the fact that it additionally comprises:
    a plurality of pathways through silicon (1120) coupling the plurality of segments of the first metallic layer located in a back-end-of-line section (606) of the chip and the plurality of segments of the second metallic layer located in a section of distributed design layer (602) of the chip to form a continuous path without intersection between the first inductor input and the second inductor input.
    [2]
    2. Chip inductor, according to claim 1, characterized by the fact that the first and second inductor inputs are located in one of the first metallic layer and the second metallic layer, and the chip inductor has a symmetrical geometry in around a line of symmetry passing between the first and second inductor inputs.
    [3]
    3. Chip inductor, according to claim 1, characterized by the fact that the chip inductor has an asymmetric geometry.
    [4]
    4. Chip inductor, according to claim 3, characterized by the fact that the first input of
    Petition 870190090562, of 12/09/2019, p. 40/47
    2/6 inductor is located in one of the first metallic layer and second metallic layer and the second inductor inlet is located in a third metallic layer.
    5. Inductor in chip, in wake up with the claim 1, characterized by fact in that plurality of routes through silicon (1120) is distributed in a pattern in regular arrangement.6. Inductor in chip, in wake up with the claim 5,
    characterized by the fact that the pattern of regular arrangement of paths through silicon (1120) is surrounded by a perimeter comprising a plurality of paths through silicon coupled to the ground.
    7. Three-dimensional chip transformer characterized by the fact that it comprises:
    a first chip inductor (1420, 1520, 1620) and a second chip inductor (1422, 1522, 1622), each of the first and second chip inductors being as defined in any of claims 1 to 6, wherein the first chip inductor (1420, 1520, 1620) is inductively coupled to the second chip inductor (1422, 1522, 1622), and the first chip inductor (1420, 1520, 1620) is not physically coupled to the second chip inductor (1422, 1522, 1622) except across the land.
    8. Three-dimensional chip radio frequency amplifier (1400, 1500, 1600), comprising:
    a first chip transformer (1402, 1502, 1602) comprising a first chip inductor (1420, 1520, 1620) and a second chip inductor (1422, 1522, 1622);
    Petition 870190090562, of 12/09/2019, p. 41/47
    3/6 a second chip transformer (1404, 1504, 1604) comprising a third chip inductor (1440, 1540, 1640) and a fourth chip inductor (1442, 1542, 1642);
    a first chip transistor comprising a port, a drain and a source;
    characterized by the fact that each of the first, second, third and fourth chip inductors comprises a plurality of first segments in a first metallic layer located in a back-of-line section of the chip; a plurality of second segments in a second metallic layer located in a distributed design layer section of the chip; a first inductor input and a second inductor input, the first and second inductor inputs being located in one of the first metallic layer and the second metallic layer; and a plurality of pathways through silicon (1120) coupling the plurality of first segments and the plurality of second segments to form a continuous path without intersection between the first inductor input and the second inductor input;
    the first chip inductor (1420, 1520, 1620) being inductively coupled to the second chip inductor (1422, 1522, 1622), the third chip inductor (1440, 1540, 1640) being inductively coupled to the fourth chip inductor (1442, 1542, 1642), and the first, second, third and fourth chip inductors are not physically coupled to each other except through the ground;
    the first inductor input of the first chip inductor (1420, 1520, 1620) being coupled to an input of the chip radio frequency amplifier (1400, 1500, 1600);
    Petition 870190090562, of 12/09/2019, p. 42/47
    4/6 the first inductor input of the second chip inductor (1422, 1522, 1622) being coupled to the port of the first chip transistor; the first inductor input of the third chip inductor (1440, 1540, 1640) being coupled to the drain of the first chip transistor, the first inductor input of the fourth chip inductor (1442, 1542, 1642) being coupled to an output of the amplifier (1400, 1500,
    1600) of radio frequency on chip; the second inductor input of the first, second, third and fourth chip inductors being coupled to the ground; and the source of the first chip transistor being coupled to the ground.
    9. Radio frequency amplifier (1400, 1500, 1600)
    on chip, in according to claim 8, featured by the fact in that the first metallic layer is located in a section in back-end-of-line (606) of the chip.10.Amplifier (1400, 1500, 1600) in
    chip radio frequency, according to claim 8, characterized by the fact that the second metallic layer is located in a redistributed design layer of the chip.
    11. Chip radio frequency amplifier (1400, 1500, 1600) according to claim 8, characterized by the fact that it additionally comprises:
    a fifth inductor including a first inductor input and a second inductor input;
    a sixth inductor including a first inductor input and a second inductor input;
    a second chip transistor including a port, a drain and a source; and
    Petition 870190090562, of 12/09/2019, p. 43/47
    [5]
    5/6 the port of the second chip transistor being coupled to the drain of the first chip transistor; the drain of the second chip transistor being coupled to the first inductor input of the third chip inductor (1440, 1540, 1640), the source of the second chip transistor being coupled to the ground; the first inductor input of the fifth and sixth chip inductors being coupled to a supply voltage; the second inductor input of the fifth chip inductor being coupled to the drain of the first chip transistor; and the second inductor input of the sixth chip inductor being coupled to the drain of the second chip transistor.
    12. Chip radio frequency amplifier (1400, 1500, 1600) according to claim 11, characterized in that the fifth chip inductor comprises a plurality of first segments in a first metallic layer, a plurality of second segments in a second metallic layer and a plurality of paths through silicon (1120) coupling the plurality of first segments and the plurality of second segments to form the continuous path without intersection between the first inductor input and the second inductor input of the fifth inductor, the first and second inductor inputs of the fifth inductor being located in one of the first metallic layer and the second metallic layer; and the sixth chip inductor comprises a plurality of first segments in a first metallic layer, a plurality of second segments in a second metallic layer and a plurality of pathways through silicon (1120) coupling the plurality of first segments and the
    Petition 870190090562, of 12/09/2019, p. 44/47
    [6]
    6/6 plurality of second segments to form a continuous path without intersection between the first inductor input and the second inductor input of the sixth inductor, the first and second inductor inputs of the sixth inductor being located in one of the first metallic layer and the second metallic layer.
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    同族专利:
    公开号 | 公开日
    JP2015019105A|2015-01-29|
    TW201135803A|2011-10-16|
    CN106847770A|2017-06-13|
    JP6076089B2|2017-02-08|
    WO2011044392A1|2011-04-14|
    US8508301B2|2013-08-13|
    BR112012007822A2|2016-03-08|
    US20120056680A1|2012-03-08|
    US8143952B2|2012-03-27|
    JP2013507774A|2013-03-04|
    TWI450316B|2014-08-21|
    JP5937166B2|2016-06-22|
    US20110084765A1|2011-04-14|
    KR20120054665A|2012-05-30|
    EP2486586B1|2020-11-18|
    ES2854713T3|2021-09-22|
    CN102576657A|2012-07-11|
    EP2486586A1|2012-08-15|
    KR101512805B1|2015-04-16|
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    法律状态:
    2019-01-08| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2019-06-18| B07A| Technical examination (opinion): publication of technical examination (opinion) [chapter 7.1 patent gazette]|
    2020-02-18| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2020-04-07| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 07/10/2010, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US12/576,033|US8143952B2|2009-10-08|2009-10-08|Three dimensional inductor and transformer|
    PCT/US2010/051868|WO2011044392A1|2009-10-08|2010-10-07|Three dimensional inductor and transformer|
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